-- $Id: $
-- File name:   DECODE.vhd
-- Created:     10/3/2010
-- Author:      Christopher Sakalis
-- Lab Section: 4
-- Version:     1.0  Initial Design Entry
-- Description: DECODE.


LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity DECODE is
    port( CLK : in std_logic;
        RST_N : in std_logic;
       D_PLUS : in std_logic;
 SHIFT_ENABLE : in std_logic;
          EOP : in std_logic;
       D_ORIG : out std_logic);
end DECODE;

architecture BEHAVIORAL of DECODE is
  signal oldBit: std_logic;
  signal NEXToldBit: std_logic;
  signal curr: std_logic;
  signal NEXTcurr: std_logic;
   Begin
     StateReg: process (CLK, RST_N)
      begin
        if (RST_N='0') then
           oldBit <= '1';
           curr <= '1';
        elsif (CLK'event and CLK='1') then
          oldBit <= NEXToldBit;
          curr <= NEXTcurr;
        end if;
     end process StateReg;


     NextReg: process (curr, oldBit, SHIFT_ENABLE, EOP, D_PLUS) --Old version: replace "NEXToldBit" with "NEXTcurr" and "curr" with "oldBit"
     begin
--        NEXToldBit <= curr;
       if (SHIFT_ENABLE = '1') then
         NEXTcurr <= D_PLUS;
         NEXToldBit <= curr;
       else
         NEXTcurr <= curr;
         NEXToldBit <= oldBit;
       --NEXToldBit <= '0';
       end if;
       if (EOP = '1') then
         NEXTcurr <= '1';
         NEXToldBit <= '1';
       end if;
     end process NextReg;


     Out_cmp: process (curr, oldBit)
     begin
       D_ORIG <= curr xnor oldBit;
     end process Out_cmp;
end BEHAVIORAL;















